Counter 101

This article describes a digital frequency display unit for the transceiver Yaesu FT-101Z.

1. Introduction

The unit is optimized for the installation of a digital frequency display into the transceiver FT101Z.
But it can also be modified to other transceivers.

In order to simplify the upgrade this circuit requires only moderate modification inside the transceiver.
The circuit operates with a single +5V supply voltage and can be realized with standard logic ICs.
The circuit does not require adjustments.

A picture of the PCB is here.

2. Circuit Concept

The principle function of this circuit is based on the function Yaesu described in [1].

A sinus input signal is converted into a duty cycle signal. 
The frequency is calculated by counting pulses during a defined gate time tG.

f = -------                (1)

f: required frequency
n: Number of counted pulses during tG
tG: Gate time

Equation (1) also shows that the accuracy of the measured frequency depends on the accuracy of the gate time.
The required frequency is derived from the premix frequency which is available on socket J01 of the premix unit 
(PB-1962). Refer to table 1 for the premix frequencies for the different bands and modes.

Band /m fLSB/MHz fUSB/MHz fCW/MHz
160 10.486 - 10.986 10.489 - 10.989 10.4883 - 10.9883
80 12.486 - 12.986 12.489 - 12.989 12.4883 - 12.9883
40 15.986 - 16.486 15.989 - 16.489 15.9883 - 16.4883
20 22.986 - 23.486 22.989 - 23.489 22.9883 - 23.4883
15 29.986 - 30.486 29.989 - 30.489 29.9883 - 30.4883
10A 36.986 - 37.486 36.989 - 37.489 36.9883 - 37.4883
10B 37.486 - 37.986 37.489 - 37.989 37.4883 - 37.9883
10C 37.986 - 38.486 37.989 - 38.489 37.9883 - 38.4883
10D 38.486 - 38.986 38.489 - 38.989 38.4883 - 38.9883

Table 1: Premix Frequencies [1]


With tG=100 ms only 1/10 of the incoming pulses are counted. This also assumes that the accuracy of the premix
frequency is within a range of ± 10 Hz. A further divider 1:10 gives the required resolution of 100 Hz.

Since the premix frequency does not represent the required n the counting result must be manipulated in such a way
that the result represents the required frequency . This manipulation can be done with a preset (equation 2).

f = -------                (2)

m: Preset for counter

Table 2 shows the preset code and for the different modes for each digit.

Mode 10M 1M 100K 10K 1K 100
LSB 9 1 0 1 4 0
USB 9 1 0 1 1 0
CW/AM 9 1 0 1 1 7

Table 2: Preset-Code for counter [1]


The system of presetting the counter can best be explained by an example.
For a frequency of f=14000 kHz CW the premix frequency is fP=22988300 Hz (table 1).
The CW preset code is m=91011700.

       22.988.300 + 91.011.700
f = -------------------------------- = 114.000.0
                10 x 10

The left hand digit "1" can be dropped (overflow) and the result frequency is 14.000.0.
This is the displayed number.


3. Circuit Description

The circuit consists of these functional parts

- Premix converter
- Gate signal Circuit
- Control signal circuit
- Counter with display circuit
- Power supply

3.1 Premix Converter

The Premix Converter converts the premix signal fP from the Premix Unit into a duty cycle signal. 
The amplified signal (T3) is fed to a waveshaper (IC36). 
The transistor T3 acts as an interface between the waveshaper and the TTL circuitry and provides the TTL signal.


3.2 Gate Signal Circuit

The Gatesignal (fG=16 MHz) is produced from the integrated crystal-controlled oszillator (IC35). 
The selection of this frequency has two advantages.
The CTRL-Signal (16 MHz) allows a quick and simple functional check of the circuit (refer section 4). 
In addition the 80 Hz G signal can be easily dissipated which is then used to create the needed control
signals (divider 1:200000 with IC29 ... IC34).


3.3 Control Signal Circuit

The G-Signal (80 Hz) is the starting point in the control signal circuit and is used to create all control signals.
The control signals are

- the gate control signal GS
- the clock signal for the registers LOAD_R
- the loading pulse for the counter LOAD_C
- the clock signal for the counter T10

The premix clock TP is fed from ST3 through an inverter (IC50) to the gate (IC24).
The gate time is set by the signal GS. The pulses passing the gate during the gate time are counted
and IC27 and IC28 then create the clock signal T10 for the counter cascade.

The schematic timing diagram shows the function.

Bild 5: Zeit-Diagramm für Steuersignal-Erzeugung (schematisch)
Timing diagram for Control Signals (schematic)

The divider 1:16 (IC22) creates pulses (t=200 ms) which open the gate for a half clock period.
During the second clock period the gate is open only for a short time (tL=25 ms).
During this time also LOAD_C is active which is used to preset the counter to the preset value S0 ... S4.
The LOAD_R signal loads the count result into the register.

IC 26 and IC27 are acting as control signals buffers for the counters and registers.

S0 ... S4 are used to set the preset code for the counters.

The signal DIGIT_10 is created from A and B (OR Gate) and disables the 10 MHz digit of the display for
frequencies below the 20m band.


3.4 Counter and Display

The counter cascade is realized with IC16 ... IC21

IC21 is used for the 100 Hz-Digit
IC20 is used for the 1 kHz-Digit
IC19 is used for the 10 kHz-Digit
IC18 is used for the 100 kHz-Digit
IC17 is used for the 1 MHz-Digit
IC16 is used for the 10 MHz-Digit

The counting result (gate time tG=100 ms) is loaded with the signal LOAD_R and buffered with the registers IC13 ... IC15.
IC7 ... IC12 convert the BCD code into the 7 segment code.

The display elements IC1 ... IC6 are on a separate PCB which is mounted behind the display window 
of the transceiver.


4. Assembly of the Circuit

The assembly is not problematic and easy. A breadbord can be used.
It is recommended to think about the positions of the elements before starting since the space inside of the radio is limited.

Here are some hints:

The output signal of the crystal oscillator provides TTL compatible signals. Therefore the first divider stage must be able to handle
the frequency and the voltage level (first divider stage in FAST followed by an ACT00).
Generally it is recommended not to use components that are not specified for these frequencies and voltage levels.

The circuit is realized on two PCBs (counter and display PCB). The display PCB is placed behind the window with small mounting holders.

The connection between the two PCBs is made with a 40 wire flat cable (ST1, ST11).
The supply voltage and the connection to the remaining diode (note that diode f of IC1 is not connected) is done separatly
(ST2, ST21 and ST9, ST91)

The supply voltage UB=+5V comes from the integrated voltage regulator.

The bridge ST3 can be used for a quick check of the correct function. If CTRL (16 MHz) is the input signal frequency the display
shows the frequency f=7.011.7 MHz (refer to section 2).

With regard to the limited space inside the radio I have developed PCBs with SMD components which are optimized for the
installation into the FT101Z.


5. Mounting into the Transceiver FT101Z

The installation into the transceiver requires a minimum of modifications inside the radio.
There are only 3 soldering actions needed. 
Concerning the disassembly of the old analogue display refer to the handbook [1].

Montage des Counter 101  in den Transceiver FT101Z

The above picture shows the position of the new counter PCB on top of the mounting frame of
PB-1962 and PB-1960. Note that this position is different from [1].

This mounting position also feed the ground signal from the metallic mounting frame to the PCB.
The display PCB is fixed on the VFO mounting frame.

The voltage regulator is mounted directly on the mounting frame of PB-1962 and PB-1960.
Use some heat sink compound for this installation.

A small piece pf coaxial cable is used to feed the premix signal from the socket J01 (PB-1962)
to the counter PCB.
The control signals USB and LSB are available on socket J01 (PB-1964, AF Unit) on the lower side
of the radio.


[1]: Instruction Manual FT-101ZD
      Yaesu Musen Co., Ltd., Tokyo, Japan


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